1. Field of the Invention
The present invention relates to an SOI single crystalline chip structure, and, more particularly, to an SOI single crystalline chip structure having a metal layer filled into at least one through hole located at a predetermined position of the embedded oxide layer, and the method of manufacturing the same.
2. Description of the Prior Art
Please refer to FIG. 1 of showing a schematic diagram of an SOI single crystalline chip structure 20 according to the prior art. The SOI chip structure 20 includes a single crystal active device layer 22, a buried oxide layer 24 (thereinafter refer to as “BOX”) under the active device layer 22, and a silicon substrate ground layer 26 under the BOX 24. This embodiment 20 further includes an interconnect layer 27 above the active device layer 22. The active device layer 22 is for the SOI device 28 layout. With the provision of conductive vias 31, the interconnect layer 27 will have the SOI device 28 grounded (i.e., voltage level of the SOI device 28 make reference to that of the silicon substrate 26 serving as a ground layer) and provide a means of heat dissipation.
The SOI device 28 will have the voltage level reference to the silicon substrate ground layer 26 with the settings of the interconnect layer 27 and the conductive vias 31 passing through the active device layer 22 and BOX 24. The conductive vias 31 connecting the interconnect layer 27 and silicon substrate ground layer 26 can provide grounding effect for the SOI device 28, but the contact resistance in this case is not as ideal as expected consequently. Moreover, the setting of BOX 24 places uncertainty to the performance of heat dissipation of the SOI device 28 to the silicon substrate ground layer 26. This may be caused by the result of the BOX 24 being an oxidation instead of a metal.